Self-Testing of S-Compatible Test Units in User-Programmed FPGAs

Self-Testing of User-Programmed FPGAs Based on the Concept of Linear Segments

Post-Programming Burn-In (PPBI) for Actel RT54SX-S and SX-A FPGAs

Burn-in (BI) for programmed Field Programmable Gate Arrays (FPGAs) is a growing concern in the space community. This application note addresses these concerns with regard to the Actel RT54SX-S and SX-A FPGA device families in an unprogrammed versus a programmed mode. This application note discusses the main differences between the architecture of the RT54SX-S and SX-A families and it describes ...

BIST-Based Delay-Fault Testing in FPGAs

We present the first delay-fault testing approach for Field Programmable Gate Arrays (FPGAs), applicable for on-line testing as well as for off-line manufacturing and system-level testing. Our approach is based on Built-In Self-Test (BIST), it is comprehensive, and does not require expensive external test equipment (ATE). We have successfully implemented this BIST approach for delay-fault testi...

Real-Time BIST Detector for BGA Faults in Field Programmable Gate Arrays (FPGAs)

In this paper we introduce a solderjoint built-in-self-test (SJ BIST) for detecting high-resistance and intermittent faults in operational, fully programmed field programmable gate arrays (FPGAs). The approach is simple to implement, offers a method to detect high-resistance faults that result from damaged solder joints, and uses a maximum of one small capacitor externally connected to each sel...

The First Clock Cycle Is A Real BIST

The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that the user can be assured that their system function is downloaded to a fault-free device. In this paper, we present case studies of developing BIST configurations for some of the less thought of, though equally importa...